Current large-scale computing systems often rely on multiple processors and memory banks for performing various computer functions and executing application programs. Data processing on such computing systems generally requires a large quantity of transaction transfers between different subsystems of the computing system, such as write/read requests for data to/from memory. Such transactions may occur concurrently, and in many cases may involve the same target memory location(s). To accommodate the orderly transfer of transactions within such multi-processing and/or multi-memory systems, the transactions may require temporary buffering, where the transactions are temporarily stored until the appropriate source or destination components are prepared to operate on the data. Traditional methods of data buffering often involve First-In, First-Out (FIFO) queues that involves the temporary storage of such transactions (and associated data where applicable) until a particular processor or memory can process the transaction.
A FIFO sends transactions in the order the transactions are received. A first transaction received by a FIFO buffer is the first transaction sent by the FIFO buffer. The priority of the first transaction compared to a second transaction may vary. For example, a low priority first transaction may be followed at a later time by a high priority second transaction that may need to be sent to a destination location in an urgent manner. Meanwhile, the destination location of the first transaction may not be ready to receive the first transaction. However, with a traditional FIFO the first transaction received by the FIFO will be the first transaction sent to its appropriate destination location. The higher-priority second transaction may be significantly delayed before arriving at its destination location.
A second approach for buffering transactions includes non-FIFO buffers with additional logic. Transactions in a non-FIFO buffer are transferred in an order determined by the additional logic as a function of the priority of the transactions. For example, high priority transactions can be transferred from the buffer prior to earlier-received low priority transactions. However, the additional logic increases circuit complexity.
Prior approaches for buffering transactions include FIFO buffers and non-FIFO buffers with additional logic. The first approach cannot distinguish between high and low priority transactions. High priority transactions are slowed by the transfer of low priority transactions previously received by the FIFO. The additional logic of the second approach requires additional design, layout, software development, and test development time. Additional layout space is also required for the additional logic resulting in less compact designs. Project development cycles are slowed by implementing the additional logic.
For many computing systems, transaction transfer efficiency related to transaction buffering directly impacts overall computing system performance. Accordingly, it would be desirable to provide an apparatus and method for addressing these needs and other challenges mentioned above.